Article
Design and Simulation of Advanced 1×4 Router Using Verilog HDL
data forwarding in Network-on-Chip (NoC) environments. The architecture steers each incoming packet toward one of four destination ports via a 2-bit address field in the packet header. Five cooperating modules — router_reg, router_fsm (8-state Moore FSM), router_sync, four 16×9 synchronous router_fifo buffers, and router_top — constitute the complete design. Reliability is ensured through an XOR parity checker and a busy back-pressure signal. Synthesised in Vivado 2025.1 on an Artix-7 FPGA (xc7a35tcpg236-1), a six-scenario self-checking testbench yielded pass_cnt = 6, fail_cnt = 0. Post-implementation resource usage remained below 1% of available Slice LUTs and Registers with zero Block RAM, confirming suitability for embedded NoC fabrics
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