Design and Simulation of Advanced 1×4 Router Using Verilog HDL

Design and Simulation of Advanced 1×4 Router Using Verilog HDL Ms. M. Usha¹ | D. Reshme² | K. Viswanth³ 03 04 data forwarding in NetworkonChip NoC environments The architecture steers each incoming packet toward one of four destination ports via a 2bit address field in the packet header Five cooperating modules routerreg routerfsm 8state Moore FSM routersync four 169 synchronous routerfifo buffers and routertop constitute the complete design Reliability is ensured through an XOR parity checker and a busy backpressure signal Synthesised in Vivado 20251 on an Artix7 FPGA xc7a35tcpg2361 a sixscenario selfchecking testbench yielded passcnt 6 failcnt 0 Postimplementation resource usage remained below 1 of available Slice LUTs and Registers with zero Block RAM confirming suitability for embedded NoC fabrics

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